# FPGA_UART

**Repository Path**: fengshuaigit/FPGA_UART

## Basic Information

- **Project Name**: FPGA_UART
- **Description**: 用verilog编写的UART源码，包含测试代码。
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 1
- **Forks**: 1
- **Created**: 2015-11-08
- **Last Updated**: 2024-01-17

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

No README documentation available for this project.